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[IEEE Comput. Soc. Press 14th VLSI Test Symposium - Princeton, NJ, USA (28 April-1 May 1996)] Proceedings of 14th VLSI Test Symposium - Enhancing realistic fault secureness in parity prediction array arithmetic operators by I/sub DDQ/ monitoring

[IEEE Comput. Soc. Press 14th VLSI Test Symposium - Princeton, NJ, USA (28 April-1 May 1996)] Proceedings of 14th VLSI Test Symposium - Enhancing realistic fault secureness in parity prediction array arithmetic operators by I/sub DDQ/ monitoring

Manich, S.; Nicolaidis, M.; Figueras, J.

作者Manich, S.; Nicolaidis, M.; Figueras, J.
文件大小525.22KB
发表时间1996
DOI10.1109/VTEST.1996.510846
页码124-129

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