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[IEEE Comput. Soc Design, Automation and Test in Europe. Conference and Exhibition 2001 - Munich, Germany (13-16 March 2001)] Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001 - Circuit partitioning for efficient logic BIST synthesis

[IEEE Comput. Soc Design, Automation and Test in Europe. Conference and Exhibition 2001 - Munich, Germany (13-16 March 2001)] Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001 - Circuit partitioning for efficient logic BIST synthesis

Irion, A.; Kiefer, G.; Vranken, H.; Wunderlich, H.-J.

作者Irion, A.; Kiefer, G.; Vranken, H.; Wunderlich, H.-J.
文件大小517.66KB
发表时间2001
DOI10.1109/date.2001.915005
页码86-91

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