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[Japan Soc. Appl. Phys 2001 Symposium on VLSI Technology. Digest of Technical Papers - Kyoto, Japan (12-14 June 2001)] 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) - Scaling towards 35 nm gate length CMOS

[Japan Soc. Appl. Phys 2001 Symposium on VLSI Technology. Digest of Technical Papers - Kyoto, Japan (12-14 June 2001)] 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) - Scaling towards 35 nm gate length CMOS

Bin Yu, ; Haihong Wang, ; Qi Xiang, ; An, J.X.; Joong Jeon, ; Ming-Ren Lin,

作者Bin Yu, ; Haihong Wang, ; Qi Xiang, ; An, J.X.; Joong Jeon, ; Ming-Ren Lin,
文件大小253.38KB
发表时间2001
DOI10.1109/vlsit.2001.934921
页码9-10

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