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[IEEE 2002 Symposium on VLSI Circuits. Digest of Technical Papers - Honolulu, HI, USA (13-15 June 2002)] 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) - A 6 GHz, 16 Kbytes L1 cache in a 100 nm dual-V/sub T/ technology using a bitline leakage reduction (BLR) technique

[IEEE 2002 Symposium on VLSI Circuits. Digest of Technical Papers - Honolulu, HI, USA (13-15 June 2002)] 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) - A 6 GHz, 16 Kbytes L1 cache in a 100 nm dual-V/sub T/ technology using a bitline leakage reduction (BLR) technique

Yibin Ye, ; Khellah, M.; Somasekhar, D.; Farhang, A.; De, V.
  • 作者Yibin Ye, ; Khellah, M.; Somasekhar, D.; Farhang, A.; De, V.
  • 文件大小191.13KB
  • 发表时间2002
  • DOI10.1109/VLSIC.2002.1015042
  • 页码50-51
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