[IEEE IEEE International Electron Devices Meeting 2003 - Washington, DC, USA (8-10 Dec. 2003)] IEEE International Electron Devices Meeting 2003 - A 65nm-node, Cu interconnect technology using porous SiOCH film (k=2.5) covered with ultra-thin, low-k pore seal (k=2.7)

Tada, M.; Harada, Y.; Tamura, T.; Inoue, N.; Ito, F.; Yoshiki, M.; Ohtake, H.; Narihiro, M.; Tagami, M.; Ueki, M.; Hijioka, K.; Abe, M.; Takeuchi, T.; Saito, S.; Onodera, T.; Furutake, N.; Arai, K.; Fujii, K.; Hayashi, Y.

作者Tada, M.; Harada, Y.; Tamura, T.; Inoue, N.; Ito, F.; Yoshiki, M.; Ohtake, H.; Narihiro, M.; Tagami, M.; Ueki, M.; Hijioka, K.; Abe, M.; Takeuchi, T.; Saito, S.; Onodera, T.; Furutake, N.; Arai, K.; Fujii, K.; Hayashi, Y.
文件大小291.91KB
发表时间2003
DOI10.1109/iedm.2003.1269411

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[IEEE IEEE International Electron Devices Meeting 2003 - Washington, DC, USA (8-10 Dec. 2003)] IEEE International Electron Devices Meeting 2003 - A 65nm-node, Cu interconnect technology using porous SiOCH film (k=2.5) covered with ultra-thin, low-k pore seal (k=2.7)