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[IEEE 2004 IEEE International Symposium on Circuits and Systems - Vancouver, BC, Canada (23-26 May 2004)] 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) - Delay bound based CMOS gate sizing technique

[IEEE 2004 IEEE International Symposium on Circuits and Systems - Vancouver, BC, Canada (23-26 May 2004)] 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) - Delay bound based CMOS gate sizing technique

Verle, A.; Michel, X.; Maurine, P.; Azemard, N.; Auvergne, D.

作者Verle, A.; Michel, X.; Maurine, P.; Azemard, N.; Auvergne, D.
文件大小315.71KB
发表时间2004
DOI10.1109/iscas.2004.1329494

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