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[IEEE Comput. Soc Design, Automation and Test in Europe Conference and Exhibition - Paris, France (16-20 Feb. 2004)] Proceedings Design, Automation and Test in Europe Conference and Exhibition - Hybrid reduction technique for efficient simulation of linear/nonlinear mixed circuits

[IEEE Comput. Soc Design, Automation and Test in Europe Conference and Exhibition - Paris, France (16-20 Feb. 2004)] Proceedings Design, Automation and Test in Europe Conference and Exhibition - Hybrid reduction technique for efficient simulation of linear/nonlinear mixed circuits

Mine, T.; Kubota, H.; Kamo, A.; Watanabe, T.; Asai, H.

作者Mine, T.; Kubota, H.; Kamo, A.; Watanabe, T.; Asai, H.
文件大小324.75KB
发表时间2004
DOI10.1109/date.2004.1269079
页码1327-1332

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