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[IEEE Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. - Napa Valley, CA, USA (Nov. 30-Dec. 2, 2005)] Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. - Formal meaning of coverage metrics in simulation-based hardware design verification

[IEEE Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. - Napa Valley, CA, USA (Nov. 30-Dec. 2, 2005)] Tenth IEEE International High-Level Design Validation and Test Workshop, 2005. - Formal meaning of coverage metrics in simulation-based hardware design verification

Ugarte, I.; Sanchez, P.

作者Ugarte, I.; Sanchez, P.
文件大小326.51KB
发表时间2005
DOI10.1109/hldvt.2005.1568841
页码221-228

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