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[IEEE Computer Soc 18th International Conference on VLSI Design - Kolkata, India (3-7 Jan. 2005)] 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design - False path and clock scheduling based yield-aware gate sizing

[IEEE Computer Soc 18th International Conference on VLSI Design - Kolkata, India (3-7 Jan. 2005)] 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design - False path and clock scheduling based yield-aware gate sizing

Jeng-Liang Tsai, ; Dong Hyun Baik, ; Chung-Ping Chen, C.; Saluja, K.K.

作者Jeng-Liang Tsai, ; Dong Hyun Baik, ; Chung-Ping Chen, C.; Saluja, K.K.
文件大小116.27KB
发表时间2005
DOI10.1109/icvd.2005.99
页码423-426

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