[IEEE 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Arlington, VA, USA (2006.10.4-2006.10.4)] 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost

• 作者Garg, Akhil; Dubey, Prashant
• 文件大小162.10KB
• 发表时间2006
• DOI10.1109/dft.2006.32
• 页码166-174