[IEEE 2007 Joint 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) and the IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007) - Montreal, QC, Canada (2007.08.5-2007.08.8)] 2007 50th Midwest Symposium on Circuits and Systems - 3.2-Gb/s 1024-b rate-1/2 LDPC decoder chip using a flooding-type update-schedule algorithm
Naoya Onizawa, ; Tomokazu Ikeda, ; Takahiro Hanyu, ; Gaudet, Vincent C.
- 作者Naoya Onizawa, ; Tomokazu Ikeda, ; Takahiro Hanyu, ; Gaudet, Vincent C.
- 文件大小378.13KB
- 发表时间2007
- DOI10.1109/mwscas.2007.4488574
- 页码217-220