[IEEE 2008 11th International Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS) - Bratislava, Slovakia (2008.04.16-2008.04.18)] 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems - SoC Symbolic Simulation: a case study on delay fault testing
- 作者Bosio, A.; Girard, P.; Pravossoudovich, S.; Bemardi, P.
- 文件大小3570.77KB
- 发表时间2008
- DOI10.1109/ddecs.2008.4538810
- 页码1-6
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