Comprehensive Analysis of Positive and Negative Bias Temperature Instabilities in High-
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/Metal Gate Stack Metal–Oxide–Silicon Field Effect Transistors with Equivalent Oxide Thickness Scaling to Sub-1 nm

Comprehensive Analysis of Positive and Negative Bias Temperature Instabilities in High- k /Metal Gate Stack Metal–Oxide–Silicon Field Effect Transistors with Equivalent Oxide Thickness Scaling to Sub-1 nm

Sato, Motoyuki; Yamabe, Kikuo; Shiraishi, Kenji; Miyazaki, Seiichi; Yamada, Keisaku; Tamura, Chihiro; Hasunuma, Ryu; Inumiya, Seiji; Aoyama, Takayuki; Nara, Yasuo; Ohji, Yuzuru

期刊名称Japanese Journal of Applied Physics
作者Sato, Motoyuki; Yamabe, Kikuo; Shiraishi, Kenji; Miyazaki, Seiichi; Yamada, Keisaku; Tamura, Chihiro; Hasunuma, Ryu; Inumiya, Seiji; Aoyama, Takayuki; Nara, Yasuo; Ohji, Yuzuru
卷第47卷
期第4期
印刷ISSN0021-4922
电子ISSN1347-4065
文件大小318.28KB
发表时间2008-4-25
DOI10.1143/JJAP.47.2354
页码2354-2359

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Comprehensive Analysis of Positive and Negative Bias Temperature Instabilities in High- k /Metal Gate Stack Metal–Oxide–Silicon Field Effect Transistors with Equivalent Oxide Thickness Scaling to Sub-1 nm