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[IEEE 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip (VLSI-SoC) - Kowloon, Hong Kong (2011.10.3-2011.10.5)] 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip - An easily testable routing architecture of FPGA

[IEEE 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip (VLSI-SoC) - Kowloon, Hong Kong (2011.10.3-2011.10.5)] 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip - An easily testable routing architecture of FPGA

Iida, Masahiro; Inoue, Kazuki; Amagasaki, Motoki; Sueyoshi, Toshinori

作者Iida, Masahiro; Inoue, Kazuki; Amagasaki, Motoki; Sueyoshi, Toshinori
文件大小1552.48KB
发表时间2011
DOI10.1109/vlsisoc.2011.6081661
页码106-109

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