[IEEE ESSCIRC 2012 - 38th European Solid State Circuits Conference - Bordeaux, France (2012.09.17-2012.09.21)] 2012 Proceedings of the ESSCIRC (ESSCIRC) - An 8bit 0.35–0.8V 0.5–30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator

• 作者Yoshioka, Kentaro; Shikata, Akira; Sekimoto, Ryota; Kuroda, Tadahiro; Ishikuro, Hiroki
• 文件大小880.87KB
• 发表时间2012
• DOI10.1109/esscirc.2012.6341365
• 页码381-384