[IEEE 2013 IEEE International Solid-State Circuits Conference (ISSCC 2013) - San Francisco, CA (2013.2.17-2013.2.21)] 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers - A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array

Peng Ou, ; Jiajie Zhang, ; Heng Quan, ; Yi Li, ; Maofei He, ; Zheng Yu, ; Xueqiu Yu, ; Shile Cui, ; Jie Feng, ; Shikai Zhu, ; Jie Lin, ; Ming'e Jing, ; Xiaoyang Zeng, ; Zhiyi Yu,

作者Peng Ou, ; Jiajie Zhang, ; Heng Quan, ; Yi Li, ; Maofei He, ; Zheng Yu, ; Xueqiu Yu, ; Shile Cui, ; Jie Feng, ; Shikai Zhu, ; Jie Lin, ; Ming'e Jing, ; Xiaoyang Zeng, ; Zhiyi Yu,
文件大小435.20KB
发表时间2013
DOI10.1109/ISSCC.2013.6487635
页码56-57

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