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[IEEE 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) - Singapore (2014.01.20-2014.01.23)] 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) - A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation

[IEEE 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) - Singapore (2014.01.20-2014.01.23)] 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) - A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation

Deng, Wei; Musa, Ahmed; Siriburanon, Teerachot; Miyahara, Masaya; Okada, Kenichi; Matsuzawa, Akira
  • 作者Deng, Wei; Musa, Ahmed; Siriburanon, Teerachot; Miyahara, Masaya; Okada, Kenichi; Matsuzawa, Akira
  • 文件大小377.66KB
  • 发表时间2014
  • DOI10.1109/aspdac.2014.6742854
  • 页码21-22
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