[IEEE 2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) - Salvador, Brazil (2015.9.1-2015.9.4)] 2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) - VLSI architecture design and implementation of a LDPC encoder for the IEEE 802.22 WRAN standard

• 作者Neto, Nelson Alves Ferreira; de Oliveira, Joaquim Ranyere S.; de Oliveira, Wagner Luiz A.; Bittencourt, Joao Carlos N.
• 文件大小2460.05KB
• 发表时间2015
• DOI10.1109/PATMOS.2015.7347589
• 页码71-76