[IEEE 2015 IEEE Custom Integrated Circuits Conference - CICC 2015 - San Jose, CA, USA (2015.9.28-2015.9.30)] 2015 IEEE Custom Integrated Circuits Conference (CICC) - A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration
Dickson, Timothy O.; Liu, Yong; Agrawal, Ankur; Bulzacchelli, John F.; Ainspan, Herschel; Toprak-Deniz, Zeynep; Parker, Benjamin D.; Meghelli, Mounir; Friedman, Daniel J.
- 作者Dickson, Timothy O.; Liu, Yong; Agrawal, Ankur; Bulzacchelli, John F.; Ainspan, Herschel; Toprak-Deniz, Zeynep; Parker, Benjamin D.; Meghelli, Mounir; Friedman, Daniel J.
- 文件大小840.24KB
- 发表时间2015
- DOI10.1109/cicc.2015.7338371
- 页码1-4