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A 1.8 pJ/bit Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration

A 1.8 pJ/bit Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration

Dickson, Timothy O.; Liu, Yong; Agrawal, Ankur; Bulzacchelli, John F.; Ainspan, Herschel A.; Toprak-Deniz, Zeynep; Parker, Benjamin D.; Beakes, Michael P.; Meghelli, Mounir; Friedman, Daniel J.
  • 期刊名称IEEE Journal of Solid-State Circuits
  • 作者Dickson, Timothy O.; Liu, Yong; Agrawal, Ankur; Bulzacchelli, John F.; Ainspan, Herschel A.; Toprak-Deniz, Zeynep; Parker, Benjamin D.; Beakes, Michael P.; Meghelli, Mounir; Friedman, Daniel J.
  • 印刷ISSN0018-9200
  • 电子ISSN1558-173X
  • 文件大小4930.04KB
  • 发表时间2016
  • DOI10.1109/JSSC.2016.2550499
  • 页码1-12
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