[IEEE 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) - Dresden, Germany (2018.3.19-2018.3.23)] 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) - VerC3: A library for explicit state synthesis of concurrent systems
- 作者Elver, Marco; Banks, Christopher J.; Jackson, Paul; Nagarajan, Vijay
- 文件大小106.13KB
- 发表时间2018
- DOI10.23919/DATE.2018.8342228
- 页码1381-1386
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