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Power efficient low latency architecture for decoder: Breaking the ACS bottleneck

Power efficient low latency architecture for decoder: Breaking the ACS bottleneck

Radha, Subramanyam; Shylu, David Sundararaj; Nagabushanam, Perattur
  • 期刊名称International Journal of Circuit Theory and Applications
  • 作者Radha, Subramanyam; Shylu, David Sundararaj; Nagabushanam, Perattur
  • 印刷ISSN0098-9886
  • 电子ISSN1097-007X
  • 文件大小2021.39KB
  • 发表时间2019-07-07
  • DOI10.1002/cta.2663
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