[IEEE 2019 Symposium on VLSI Technology - Kyoto, Japan (2019.6.9-2019.6.14)] 2019 Symposium on VLSI Technology - A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm
Pal, Subhankar; Park, Dong-hyeon; Feng, Siying; Gao, Paul; Tan, Jielun; Rovinski, Austin; Xie, Shaolin; Zhao, Chun; Amarnath, Aporva; Wesley, Timothy; Beaumont, Jonathan; Chen, Kuan-Yu; Chakrabarti, Chaitali; Taylor, Michael; Mudge, Trevor; Blaauw, David; Kim, Hun-Seok; Dreslinski, Ronald
- 作者Pal, Subhankar; Park, Dong-hyeon; Feng, Siying; Gao, Paul; Tan, Jielun; Rovinski, Austin; Xie, Shaolin; Zhao, Chun; Amarnath, Aporva; Wesley, Timothy; Beaumont, Jonathan; Chen, Kuan-Yu; Chakrabarti, Chaitali; Taylor, Michael; Mudge, Trevor; Blaauw, David; Kim, Hun-Seok; Dreslinski, Ronald
- 文件大小1689.72KB
- 发表时间2019
- DOI10.23919/VLSIT.2019.8776507