[IEEE 2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) - Salvador, Brazil (2015.9.1-2015.9.4)] 2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) - VLSI architecture design and implementation of a LDPC encoder for the IEEE 802.22 WRAN standardNeto, Nelson Alves Ferreira; de Oliveira, Joaquim Ranyere S.; de Oliveira, Wagner Luiz A.; Bittencourt, Joao Carlos N. · 2015

Predicting a chaotic time series using a fuzzy neural networkL.P. Maguire; B. Roche; T.M. McGinnity; L.J. McDaid · 1998

Novel architecture and synapse design for hardware implementations of neural networksT.M. McGinnity; B. Roche; L.P. Maguire; L.J. McDaid · 1998

The implementation of fuzzy systems, neural networks and fuzzy neural networks using FPGAsJ.J. Blake; L.P. Maguire; T.M. McGinnity; B. Roche; L.J. McDaid · 1998